1. Field of the Invention
This invention relates to an analog to digital converting device, and more particularly to an analog to digital converting device of the type which includes a double integration analog to digital converter.
2. Description of the Prior Art
A conventional analog to digital converting device of the type mentioned includes in most cases a plurality of double integration analog to digital converters each of which includes an integrating circuit consisting of an operational amplifier, an integrating capacitor connected between input and output terminals of the operational amplifier, and a reset switch connected in parallel to the integrating capacitor, a comparator connected to an output terminal of the integrating circuit, an integration switch for supplying a signal to the integrating circuit to start an integrating operation of the integrating circuit, and an inverse integration switch for causing the integrating circuit to start an inverse integrating operation. A controller of the analog to digital converting device controls the reset switch, the integration switch and the inverse integration switch to operate in this order.
An example of the analog to digital converting devices of the type mentioned is illustrated in FIG. 1. Referring to FIG. 1, the analog to digital converting device shown includes a pair of double integration analog to digital converters AD.sub.1, AD.sub.2. Each of the double integration analog to digital converters AD.sub.1, AD.sub.2 includes an integrating circuit INT.sub.1, INT.sub.2, a comparator COM.sub.1, COM.sub.2 having a non-inverting input terminal (+) connected to an output terminal of the integrating circuit INT.sub.1, INT.sub.2, an integration switch IS.sub.1, IS.sub.2 for delivering an input signal V.sub.1, V.sub.2 to the integrating circuit INT.sub.1, INT.sub.2 to cause the latter to start an integrating operation, an inverse integration switch AIS.sub.1, AIS.sub.2 for causing the integrating circuit INT.sub.1, INT.sub.2 to start an inverse integrating operation, and a constant-current circuit CI.sub.1, CI.sub.2 connected to the inverse integration switch AIS.sub.1, AIS.sub.2, respectively. A resistor R.sub.1, R.sub.2 is connected to the integration switch IS.sub.1, IS.sub.2, respectively.
Each of the integrating circuits INT.sub.1, INT.sub.2 includes an operational amplifier OP.sub.1, OP.sub.2, an integrating capacitor C.sub.1, C.sub.2 connected between an inverting input terminal (-) and an output terminal of the operational amplifier OP.sub.1, OP.sub.2, and a reset switch RS.sub.1, RS.sub.2 connected in parallel to the integrating capacitor C.sub.1, C.sub.2, respectively.
The characteristics of the two double integration analog to digital converters AD.sub.1, AD.sub.2 having the construction described above are similar to each other.
The device shown in FIG. 1 further includes a controller CONT for controlling the reset switches RS.sub.1, RS.sub.2, the integration switches IS.sub.1, IS.sub.2 and the inverse integration switches AIS.sub.1, AIS.sub.2 to turn on in this order.
Counters COUN.sub.1, COUN.sub.2 are connected to output terminals of the double integration analog to digital converters AD.sub.1, AD.sub.2, respectively, and a clock generator TM is connected to deliver reference clock signals to the controller CONT and the counters COUN.sub.1, COUN.sub.2.
The controller CONT executes following operations in a sequential cyclical manner:
(1) to deliver a reset signal Q.sub.3 to the reset switches RS.sub.1, RS.sub.2 at a time just when analog to digital conversion is completed on both of the double integration analog to digital converters AD.sub.1, AD.sub.2 ;
(2) after lapse of a predetermined interval of time after starting of delivery of the reset signal Q.sub.3, to stop delivery of the reset signal Q.sub.3 and deliver an integrating signal Q.sub.1 simultaneously to both of the integration switches IS.sub.1, IS.sub.2 ;
(3) after the lapse of another predetermined interval of time after starting of delivery of the integrating signal Q.sub.1, to stop delivery of the integrating signal Q.sub.1, deliver an inverse integrating signal Q.sub.2 simultaneously to both of the inverse integration switches AIS.sub.1, AIS.sub.2 and deliver a counting start signal simultaneously to both of the counters COUN.sub.1, COUN.sub.2 ; and (4) at a time just when analog to digital conversion is completed on the double integration analog to digital converter AD.sub.1, to deliver a latch signal to the counter COUN.sub.1, and then at a time just when analog to digital conversion is completed on the double integration analog to digital converter AD.sub.2, to deliver a latch signal to the counter COUN.sub.2.
Now, operation of the analog to digital converting device will be described.
(I) When the input signals V.sub.1, V.sub.2 are equal to each other:
Referring to FIG. 2, when the controller CONT stops, at a time t.sub.1, delivery of a reset signal Q3 to both of the double integration analog to digital converters AD.sub.1, AD.sub.2 and delivers an integrating signal Q.sub.1, the integration switches IS.sub.1, IS.sub.2 are turned on so that input signals V.sub.1, V.sub.2 are delivered to the integrating circuits INT.sub.1, INT.sub.2 via the resistors R.sub.1, R.sub.2, respectively. Consequently, charging of the integrating capacitors C.sub.1, C.sub.2 in the negative polarity is started, and accordingly the outputs V.sub.INT1, V.sub.INT2 of the integrating circuits INT.sub.1, INT.sub.2 thereafter decrease linearly. Since the outputs V.sub.INT1, V.sub.INT2 are lower than 0 volts, outputs of the comparators COM.sub.1, COM.sub.2 both present an "L" (low) level.
Then at a time t.sub.2, the delivery of the integrating signal Q.sub.1 is stopped and an inverse integrating signal Q.sub.2 is delivered while at the same time a counting start signal is delivered. In response to the inverse integrating signal Q.sub.2, the inverse integration switches AIS.sub.1, AIS.sub.2 are turned on so that the charge accumulated in the integrating capacitors C.sub.1, C.sub.2 is discharged therefrom via the constant-current circuits CI.sub.1, CI.sub.2. In particular, as an inverse integrating operation, charge of the positive polarity is accumulated in the integrating capacitors C.sub.1, C.sub.2 so that the outputs V.sub.INT1, V.sub.INT2 of the integrating circuits INT.sub.1, INT.sub.2 increase linearly. However, since the outputs V.sub.INT1, V.sub.INT2 still remain lower than 0 volts, the outputs of the comparators COM.sub.1, COM.sub.2 maintain the "L" level thereof.
Meanwhile, in response to the counting start signal, the counters COUN.sub.1, COUN.sub.2 start counting of clock signals from the clock generator TM. The counting operation is performed only during a limited period of time while the outputs of the comparators COM.sub.1, COM.sub.2 maintain the "L" level.
As a result of the inverse integrating operation, the outputs V.sub.INT1, V.sub.INT2 of the integrating circuits INT.sub.1, INT.sub.2 finally reach a voltage of 0 volts particularly at the same point of time. Thus, at the time t.sub.3 when the outputs V.sub.INT1, V.sub.INT2 of the integrating circuits INT.sub.1, INT.sub.2 reach 0 volts, the outputs of the comparators COM.sub.1, COM.sub.2 are received and now present an "H" (high) level. The outputs of the comparators COM.sub.1, COM.sub.2 of the "H" level are delivered as latch signals to the counters COUN.sub.1, COUN.sub.2, respectively. At the same time, the delivery of the inverse integrating signal Q.sub.2 is stopped and a reset signal Q.sub.3 is delivered from the controller CONT to the reset switches RS.sub.1, RS.sub.2.
Thus, the reset switches RS.sub.1, RS.sub.2 are turned on in response to the reset signal Q.sub.3 so that the charge accumulated in the integrating capacitors C.sub.1, C.sub.2 is discharged at a moment. Consequently, the outputs V.sub.INT1, V.sub.INT2 of the integrating circuits INT.sub.1, INT.sub.2 are reduced and thereafter maintained to 0 volts. Meanwhile, in response to the latch signal, the counters COUN.sub.1, COUN.sub.2 latch their respective values then which indicate numbers of clock pulses and hence an interval of time from the time t.sub.2 to the time t.sub.3.
Then at a time t.sub.4 after lapse of a predetermined interval of time after the time t.sub.3, an integrating operation, that is, charging of the integrating capacitors C.sub.1, C.sub.2, is resumed.
(II) When the input signals V.sub.1, V.sub.2 are different from each other:
Operation when an input signal V.sub.2 is smaller than another input signal V.sub.1 will be described, for example, with reference to a time chart of FIG. 3.
At a time t.sub.11 at which an integrating signal Q.sub.1 is developed, charging of the integrating capacitors C.sub.1, C.sub.2 in the negative polarity is started, and consequently the outputs V.sub.INT1, V.sub.INT2 of the integrating circuits INT.sub.1, INT.sub.2 thereafter decrease. However, since the input signal V.sub.2 is smaller than the other input signal V.sub.1, the decreasing ratio of the output V.sub.INT2 is lower than the decreasing ratio of the output V.sub.INT1. Accordingly, at a time t.sub.12 when an inverse integrating signal Q.sub.2 is produced, the decreased amount of the output V.sub.INT2 from 0 volts is smaller than that of the output V.sub.INT1.
To the contrary, in an inverse integrating operation, the increasing ratio of the output V.sub.INT2 is equal to that of the output V.sub.INT1 because discharging of the charge accumulated in the integrating capacitors C.sub.1, C.sub.2 is performed both with the same constant current i.sub.r via the constant-current circuits CI.sub.1, CI.sub.2, respectively. Accordingly, the output V.sub.INT2 reaches 0 volts in advance of the other output V.sub.INT1 by an interval of time t.sub.a in FIG. 3. In particular, the output V.sub.INT2 reaches 0 volts at a time t.sub.13, and then at a time t.sub.15, the output V.sub.INT1 at last reaches 0 volts.
However, where input signals V.sub.1, V.sub.2 are different from each other, the conventional analog to digital converting device described above presents following problems.
In particular, a reset signal Q.sub.3 is produced just when the outputs V.sub.INT1, V.sub.INT2 of both of the integrating circuits INT.sub.1, INT.sub.2 reach 0 volts. Accordingly, a reset signal Q.sub.3 is not produced until after the time t.sub.15 while output of an inverse integrating signal Q.sub.2 continues till then.
Accordingly, there is no problem with the integrating circuit INT.sub.1, but in the case of the integrating circuit INT.sub.2, the inverse integrating operation continues even after the output V.sub.INT2 thereof has reached 0 volts. Accordingly, charging of the integration capacitor C.sub.2 in the positive polarity is continued so that, at the time t.sub.15 at which a reset signal Q.sub.3 is developed, a considerable amount of charge of the positive polarity is accumulated in the integrating capacitor C.sub.2. Accordingly, at a time t.sub.16 at which the delivery of the reset signal Q.sub.3 is stopped, some percent of the charge accumulated in the integrating capacitor C.sub.2 just before production of the reset signal Q.sub.3 will be restored in the integrating capacitor C.sub.2 due to dielectric absorption of the same.
Consequently, even at the time t.sub.16 at which the production of the reset signal Q.sub.3 is stopped and the integrating signal Q.sub.1 is produced, the output V.sub.INT2 of the integrating circuit INT.sub.2 is not equal to 0 volts but has a positive value .alpha.. As a result, the time at which the output of the comparator COM.sub.1 is changed over to the "L" level is t.sub.16 whereas the time at which the output of the comparator COM.sub.2 is changed over to the "L" level is t.sub.17, yielding a difference t.sub.b in time between them.
The difference in time will cause an error in the period of time over which the comparator COM.sub.2 is to continue to deliver its output in a subsequent next cycle of analog to digital conversion and finally cause an error in the count value of the counter COUN.sub.2. In particular, the output V.sub.INT2 of the integrating circuit INT.sub.2 must by nature present such a change as indicated by a chain line in FIG. 3. In such a case, the time t.sub.14 at which the output V.sub.INT2 reaches 0 volts is delayed by the time t.sub.b from the time t.sub.13 as provided by the solid line. More precisely, despite that the counter COUN.sub.2 must continue its counting operation even during the period of time t.sub.b, actually the counting operation comes to an end at the time t.sub.13.
In other words, the counter COUN.sub.1 presents a count value as counted from the time t.sub.12 to the time t.sub.15 while the output of the comparator COM.sub.1 maintains the "L" level, and thus corresponds to the input signal V.sub.1. To the contrary, the counter COUN.sub.2 presents a count value as counted from the time t.sub.12 to the time t.sub.13 while the output of the comparator COM.sub.2 maintains the "L" level. Accordingly, the count value of the counter COUN.sub.2 is smaller than a correct count value as counted naturally from the time t.sub.12 to the time t.sub.14 and does not, therefore, correspond to the input signal V.sub.2.
Such an error will increase as the difference between the input signals V.sub.1 and V.sub.2 increases.
Various countermeasures have been proposed to resolve the problem. They are, for example,
(1) to employ an integrating capacitor which has a low dielectric absorption characteristic such as a mica capacitor;
(2) to elongate the resetting time for an integrating capacitor; or
(3) to connect a latch circuit to an output terminal of a comparator to adjust a time at which an inverse integrating signal Q.sub.2 is to be developed.
However, the countermeasure as listed (1) above has a drawback that the overall capacity of the capacitor may be too great or else the capacitor may not have a sufficient capacity. Meanwhile, the countermeasure (2) has another drawback that too much time is required for analog to digital conversion and accordingly the efficiency is low. Now, the countermeasure (3) will be described with reference to FIGS. 4 and 5 in which an exemplary one of such countermeasures is illustrated.
A latch circuit LA is connected to an output terminal of a comparator COM of a double integration analog to digital converting circuit AD and delivers a signal of an "H" level to an AND gate AND.sub.1 when the output of the comparator COM is at an "L" level. During an inverse integrating operation, an inverse integrating signal Q.sub.2 which is directly delivered from a controller CONT presents the "H" level, and accordingly a final inverse integrating signal Q.sub.2 ' to an inverse integrating switch AIS also maintains the "H" level so that the inverse integrating operation is continued.
However, if the output V.sub.INT of an integrating circuit INT reaches 0 volts and consequently the controller CONT detects a change-over of the output of the comparator COM from the "L" to the "H" level and delivers a latch signal to the latch circuit LA, the latch circuit LA now delivers a signal of the "L" level to the AND gate AND.sub.1. Consequently, the final inverse integrating signal Q.sub.2 ' to the inverse integration switch AIS is changed over to the "L" level so that the inverse integration switch AIS is turned off thereby to stop the inverse integrating operation. Accordingly, the output V.sub.INT of the integrating circuit INT will thereafter maintain 0 volts and will never present a voltage higher than 0 volts. Thus, excessive charging of an integrating capacitor C in the integrating circuit INT which is connected to receive a smaller input signal is prevented and no dielectric absorption appears. Accordingly, appearance of an error in the count value of a counter is prevented.
In this instance, however, in case a latch signal is produced in response to a noise N as indicated by a broken line in FIG. 5 during an inverse integrating operation, a count value then will be latched and the final inverse integrating signal Q.sub.2 ' will be changed into the "L" level to stop the inverse integrating operation before a point of time at which the final inverse integrating signal Q.sub.2 ' is naturally to be changed into the "L" level. Consequently, before the output V.sub.INT of the integrating circuit INT reaches 0 volt, it stops its increase so that the output of the comparator COM will thereafter continue its "L" level condition. Accordingly, it is a problem that a counter may present an extraordinarily small wrong count value.